Partial block erase architecture for flash memory

ABSTRACT

A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/785,099, filed May 21, 2010, which is a divisional of U.S.application Ser. No. 11/779,685, filed Jul. 18, 2007, now issued as U.S.Pat. No. 7,804,718 on Sep. 28, 2010, which claims the benefit ofpriority of U.S. Provisional Patent Application No. 60/893,432 filedMar. 7, 2007, and U.S. Provisional Patent Application No. 60/914,849filed Apr. 30, 2007, which are incorporated herein by reference.

BACKGROUND

Flash memory is a commonly used type of non-volatile memory inwidespread use as mass storage for consumer electronics, such as digitalcameras and portable digital music players for example. The density of apresently available flash memory chip can be up to 32 Gbits (4 GB),which is suitable for use in popular USB flash drives since the size ofone flash chip is small.

FIG. 1 is a general block diagram of typical flash memory of the priorart. flash memory 10 includes logic circuitry such as control circuit12, for controlling various functions of the flash circuits, registersfor storing address information, data information and command datainformation, high voltage circuits for generating the required programand erase voltages, and core memory circuits such as row address decoder14 and row address decoder buffer 16 for accessing the memory array 18.The control circuit 12 includes a command decoder and logic forexecuting the internal flash operations, such as read, program and erasefunctions. The functions of the shown circuit blocks of flash memory 10are well known in the art. Persons skilled in the art will understandthat flash memory 10 shown in FIG. 1 represents one possible flashmemory configuration amongst many possible configurations.

The memory cell array 18 of the flash memory 10 of FIG. 1 consists ofany number of banks, which is a selected design parameter for aparticular flash device. FIG. 2 is a schematic illustration showing theorganization of one bank 20 of the memory cell array 18 of FIG. 1. Bank20 is organized as blocks (Block[0] to Block[k]), and each blockconsists of pages (WL₀ to WL_(i)). Both k and i are non-zero integervalues. Each page corresponds to a row of memory cells coupled to acommon wordline. A detailed description of the memory cells of the blockfollows.

Each block consists of NAND memory cell strings, having flash memorycells 22 serially coupled arranged and electrically coupled to eachother. Accordingly, wordlines WL₀ to WL_(i) are coupled to the gates ofeach flash memory cell in the memory cell string. A string select device24 coupled to signal SSL (string select line) selectively connects thememory cell string to a bitline 26, while a ground select device 28coupled to signal GSL (ground select line) selectively connects thememory cell string to a source line, such as VSS. The string selectdevice 24 and the ground select device 28 are n-channel transistors.

Bitlines 26 (BL₀ to BL_(j), where j is a non-zero integer value) arecommon to all blocks of bank 20, and each bitline 26 is coupled to oneNAND memory cell string in each of blocks [0] to [k]. Each wordline (WL₀to WL_(i)), SSL and GSL signal is coupled to the same correspondingtransistor device in each NAND memory cell string in the block. As thoseskilled in the art should be aware, data stored in the flash memorycells along one wordline is referred to as a page of data.

Coupled to each bitline outside of the bank 20 is a data register 30 forstoring one page of write data to be programmed into one page of flashmemory cells. Data register 30 also includes sense circuits for sensingdata read from one page of flash memory cells. During programmingoperations, the data registers perform program verify operations toensure that the data has been properly programmed into the flash memorycells coupled to the selected wordline. To achieve high density, eachflash memory cell will store at least two bits of data, and is generallyreferred to as a multi-bit-cell (MBC).

Those skilled in the art will understand that an issue with MBC flashmemory is the sensitivity of its memory cells to program disturb.Program disturb results from the capacitive coupling between adjacentwordlines and floating gates, which are formed closer to each other witheach fabrication technology generation. Hence, high voltages applied toone cell during programming can shift a programmed threshold voltage ofan adjacent cell to one representing a different logic state, while theprogrammed state of one cell can affect the threshold voltage of anadjacent cell currently being programmed. To minimize program disturb inMBC flash memory, programming within a block will start at the pagecorresponding to WL₀, and proceed sequentially up to WL_(i).Alternately, programming can start at WL_(i) and proceed sequentiallydown to WL₀. These schemes for programming NAND MBC flash memory cellsare well known in the industry. Once the block has been fully programmedwith data, programming of the next file or set of data begins at WL₀ ofthe next block. Within a device, blocks are typically programmed insequence.

It is well known that flash memory devices have a limited number oferase-program cycles before they can no longer be used to store datareliably. More specifically, flash memory cells are subject toprogram/erase cycle wearing, which is a progressive degradation of aflash memory cell due to cumulative program and erase operations. Thoseskilled in the art will understand that a memory block is always erasedfirst prior to being programmed with data, hence the cycles can bereferred to as both program and erase cycles. All currently known flashmemory is configured for block erase, meaning that if just one page ofdata in a block is to be modified/updated, the entire block containingthat page is erased and re-programmed with the modified page and theunmodified pages. The effect of such cumulative program and eraseoperations is the alteration of the program and erase characteristics ofthe memory cell beyond optimal parameters. When memory cells aredegraded, higher program and erase voltages are needed to program orerase the memory cells to the desired threshold voltages. Eventually,the memory cells will fail to retain data properly, which is representedas a programmed threshold voltage. For example, the typicalerase-program cycles for an MBC flash memory is about 10,000 cycles.

Currently, most flash memory available is of the MBC type due to thelarge storage density relative to its chip size. While this is suitablefor most consumer applications, the 10,000 cycle program-erase limit maybe insufficient for other applications where data programming anderasing is frequent. Therefore, when an MBC flash memory has reached its10,000 cycle life span, it is no longer usable and must be discarded.This problem is more critical for commercial applications, such as HDDapplications, where there are more frequent program-erase cycles.Because HDD applications require higher data integrity than mostconsumer applications, MBC flash memory is not suited for use due to itsrelatively short 10,000 cycle life span.

This problem is compounded by the fact that the block size of flashmemory devices continues to increase while the data file sizes beingstored remain relatively static. For example, block sizes for presentday high density flash devices are in the range of 256 KB, but futurehigh density flash devices will have block sizes approaching 512 KB. Ifthe data file stored in the block is small, then more memory cells willbe unnecessarily subjected to erase/program cycles relative to a blockhave the size when the data file is modified.

It is, therefore, desirable to provide a flash memory device operable tohave an extended life span.

SUMMARY

It is an aspect of the present embodiments to obviate or mitigate atleast one disadvantage of previous flash memory systems.

In a first aspect, there is provided a flash memory device having amemory array and row circuitry. The memory array has at least one blockof NAND flash memory cell strings arranged in columns, where the atleast one block has a preset number of flash memory cells beingselectively erasable. The row circuitry drives first wordlinescorresponding to the preset number of flash memory cells to a firstvoltage when the substrate is biased to an erase voltage for erasing thepreset number of flash memory cells. The row decoders drive secondwordlines to a second voltage for inhibiting erasure of the flash memorycells coupled to the second wordlines. According to embodiments of thefirst aspect, the preset number of flash memory cells can bemulti-bit-cells (MBC), they can correspond to one sequential set offlash memory cells, or they can correspond to two sequential sets offlash memory cells, where the two sequential sets of flash memory cellsare non-adjacent to each other. In another embodiment of the presentaspect, the NAND flash memory cell strings of the at least one block arecoupled to a common source line, and the flash memory device furtherincludes a source line voltage control circuit for setting a voltage ofthe common source line between a third voltage and a fourth voltageduring an erase verify operation. The fourth voltage is less than thethird voltage, and the voltage of the common source line decreases as anumber of first wordlines increases.

In a second aspect, there is provided a method for erasing a sub-blockof a memory block, where the memory block has a NAND memory cell stringcoupled to a first wordline, a last wordline, and intermediate wordlinesbetween the first wordline and the last wordline. The method includesissuing a first input address command with a first address; issuing asecond input address command with a second address; issuing a partialerase command; and erasing the sub-block having a set of wordlines boundby wordlines corresponding to the first address and the second address.

According to an embodiment of the present aspect, the first addressincludes a null address and the sub-block includes the set of wordlinesbound by one wordline corresponding to the second address and the firstwordline. In another embodiment of the present aspect, the secondaddress includes a null address and the sub-block includes the set ofwordlines bound by one wordline corresponding to the first address andthe last wordline. In yet another embodiment, the method furtherincludes erase verifying the erased sub-block. Erase verifying includesprecharging a bitline, biasing the set of wordlines, biasing unselectedwordlines, and sensing. The step of precharging includes precharging abitline coupled to the NAND memory cell string to a precharge voltagelevel. The set of wordlines are biased to a first voltage for turning onerased memory cells coupled to the set of wordlines. The unselectedwordlines are biased to a second voltage for turning on memory cellscoupled to the unselected wordlines. Sensing includes sensing a changein the precharge voltage level.

In yet a further embodiment, the first voltage is a negative voltage andthe second voltage is a read voltage used during a read operation.Alternately, the first voltage can be 0V while the second voltage is aread voltage used during a read operation. In another embodiment, acommon source line coupled to the NAND memory cell string is biased to avariable source bias voltage, which increases from 0V to a maximumvoltage as a number of the set of wordlines decreases.

In a third aspect, there is provided a method for wear leveling controlwhen modifying data in a sub-block of a memory block. The methodincludes programming modified data to an empty sub-block of a new memoryblock and erasing the sub-block of the memory block. In one embodiment,the method further includes programming new data to a lowest rankingavailable sub-block, where each memory block includes at least twosub-blocks and the lowest ranking available sub-block includes a set ofwordlines most proximate to a first wordline to be programmed in asequential programming scheme. In another embodiment, the methodincludes updating an address mapping table to map a logical address ofthe modified data to a physical address corresponding to the emptysub-block of the new memory block. In yet other embodiments, the emptysub-block is a lowest ranking available sub-block or has a ranking equalto the sub-block. When the ranking of the empty sub-block is equal tothe sub-block, the new memory block is empty or includes other datastored in another sub-block having a lower ranking than the emptysub-block. Alternately, the empty sub-block has a ranking higher thanthe sub-block. In yet a further embodiment, the method includes swappingdata in the sub-block with other data in one other sub-block of thememory block when a difference between program/erase cycles of thesub-block and the one other sub-block reaches a predetermined value.

Other aspects and features of the described embodiments will becomeapparent to those ordinarily skilled in the art upon review of thefollowing description of specific embodiments in conjunction with theaccompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments will now be described, by way of example only, withreference to the attached Figures, wherein:

FIG. 1 is a block diagram of typical flash memory of the prior art;

FIG. 2 is a diagram showing a physical arrangement of a memory array;

FIG. 3 is a conceptual illustration of partially erased physical memoryblock of a flash memory device;

FIG. 4 is a circuit schematic showing circuit details of a physicalmemory block of a flash memory array;

FIG. 5 is a graph illustrating the relationship between a source linevoltage and the number of selected wordlines during an erase verifyoperation;

FIG. 6 is a flow chart of a method for partial block erase and eraseverify;

FIGS. 7 a, 7 b and 7 c are circuit schematics of a NAND memory cellstring illustrating examples of selectively erasable sub-blocks;

FIG. 8 is a flow chart illustrating a command protocol for erasing asub-block of a memory block;

FIG. 9 is a flow chart of a method for erasing either an uppersub-block, a lower sub-block, or a sub-block slice using the commandprotocol shown in FIG. 8;

FIGS. 10 a and 10 b are schematics of memory blocks with differentlogical sub-block configurations;

FIG. 11 is a flow chart of a wear leveling algorithm;

FIG. 12 is a sub-block allocator sub-routine of the wear levelingalgorithm shown in FIG. 11;

FIGS. 13 a, 13 b, 13 c and 13 d are graphical illustrations of datare-programming to another sub-block;

FIG. 14 is a flow chart of a method for controlling program/erase cycleimbalance between sub-blocks of a memory block; and,

FIGS. 15 a and 15 b are graphical illustrations of a memory block beforeand after data swapping using the method of FIG. 14.

DETAILED DESCRIPTION

Generally, the embodiments provide a method and system for increasingthe lifespan of a flash memory device. Each physical memory block of theflash memory device is dividable into at least two logical sub-blocks,where each of the at least two logical sub-blocks are erasable.Therefore, only the data of the logical block is erased and reprogrammedwhile unmodified data in the other logical block avoids unnecessaryprogram/erase cycles. The logical sub-blocks to be erased aredynamically configurable in size and location within the block. A wearleveling algorithm is used for distributing data throughout the physicaland logical sub-blocks of the memory array to maximize the lifespan ofthe physical blocks.

FIG. 3 is a conceptual illustration of physical memory blocks (Block[0]to Block[k]) of a flash memory device, according to a presentembodiment. Each physical block can have logical sub-blocks selectivelyerased, where the sub-blocks being erased can consist of any number ofpages. In FIG. 3, portions of the memory blocks storing data are shownwith cross-hatch lines, while erased sub-blocks of the memory blockshave no cross-hatching. The size of the sub-block being selectivelyerased can be preset to be any proportion of the physical block, or canbe dynamically configurable on the fly. In the example of FIG. 3,Block[0] has a smaller erased sub-block than Block[1]. Depending on thephysical block size, it may be convenient to divide the physical blockinto more than two logical sub-blocks, such as four logical sub-blocksfor example. Hence, each physical block is partially erasable. It isassumed that the memory cells of each physical block are arranged inNAND memory cell strings, as shown in FIG. 2, and each page isprogrammed sequentially in the direction from WL₀ to WL_(i), whereWL_(i) is the last wordline to be programmed.

In the present example where data is sequentially programmed from WL₀ toWL_(i), there will be a lower sub-block and an upper sub-block. Thelower sub-block will include a lower sequential set of wordlines, whilethe upper sub-block will include a higher sequential set of wordlines.In order to minimize program disturb, the upper sub-block of any memoryblock will be erased and reprogrammed while the data of the lowersub-blocks is retained. This scheme mimics the situation where apreviously erased physical block is sequentially programmed up to acertain page, leaving the remaining pages in the erased state.Therefore, program disturb is minimized when data is later programmedsequentially to the erased upper sub-block. While a lower sub-block canbe erased while data is retained in an adjacent upper sub-block, datashould not be reprogrammed to the lower sub-block until the adjacentupper sub-block is erased.

Now that the general concept for partially erasing a physical block hasbeen introduced, further detailed embodiments will be described withreference to FIG. 4. FIG. 4 is a circuit schematic showing a physicalblock 100 of a flash memory array, a wordline driver block 102 and asource line voltage control circuit 104. The wordline driver block 102and source line voltage control circuit 104 are typically local to thephysical block 100. Physical block 100 has NAND flash memory cellstrings arranged in columns, where each string is coupled to a bitline,BL₀ to BL_(j), and a common source line CSL. The wordline driver block102 couples signal SS to the SSL control line, S[0:n] to the WL₀ toWL_(n) wordlines respectively, and GS to GSL control line. Signals SS,S[0:n] and GSL are set to a different voltage levels during program,program verify, read, and erase operations, as is well known by thoseskilled in the art. The source line voltage control circuit 104 isresponsible for setting the voltage level of CSL depending on one of theaforementioned operations being executed.

Following is an example scenario to illustrate the logical formation ofan erasable sub-block of physical block 100. It is assumed that allpages (WL₀ to WL_(n)) of physical block 100 has been programmed withdata in the direction from WL₀ to WL_(n), and the data stored in thememory cells coupled to WL₂₇ to WL_(n) is to be modified. Accordingly,the bitlines, wordlines WL₂₇ to WL_(n), and the source line CSL arebiased to erase only the data stored in the memory cells coupled towordlines WL₂₇ to WL_(n). Then the modified data is reprogrammed to thesame wordlines. The pages corresponding to wordlines WL₂₇ to WL_(n) arereferred to as an upper sub-block 106 and the pages corresponding to WL₀to WL₂₆ are referred to as a lower sub-block 108. The upper sub-block106 is therefore dynamically configurable in size, since its sizedepends on the data being erased. Alternately, the size of the sub-block106 and of sub-block 108 can be fixed.

The presently described embodiments are not limited to erase andreprogram of a sub-block, since data does not necessarily have to bereprogrammed after the sub-block is erased. This means that once asub-block is erased in one operation, any number of sequential pagesbelow the erased sub-block can be erased in a later operation, therebyextending the size of the erased sub-block.

As previously mentioned, specific pages of the physical block are erasedby biasing the bitlines, selected and unselected wordlines, and thesource line. Tables 1 and 2 provides example bias conditions effectivefor erasing a sub-block of pages in a selected physical block and biasconditions effective for inhibiting erasing in an unselected physicalblock.

TABLE 1 Selected Block Unselected Block Bitlines (B/L) Clamped toClamped to Vers-0.6 V Vers-0.6 V String Select Line (SSL) Vers Boostedto approx. 90% of Vers Selected Wordline 0 V Boosted to approx. 90% ofVers Unselected Wordline Vers Boosted to approx. 90% of Vers GroundSelect Line (GSL) Vers Boosted to approx. 90% of Vers Common Source LineClamped to Clamped to Vers-0.6 V (CSL) Vers-0.6 V Substrate (PocketP-Well) Vers Vers

In the example of Table 1, unselected wordlines are biased to a positivevoltage for preventing the corresponding unselected page(s) from beingerased. This voltage is referred to as Vers. The selected wordlines arebiased to another voltage for erasing the selected page(s), for example,0V. With the substrate of the memory cells biased to a positive voltage,such as Vers, an electrical field between the memory cells biased to 0Vand the substrate will be formed, which is effective for erasing thememory cells. The electrical field between the memory cells biased toVers and the substrate will be insufficient for erasing the memorycells, therefore erasure is inhibited and data stored therein isretained.

To prevent erasure of memory cells in unselected blocks, all wordlinesin the unselected blocks are left to float during erase operations. Thefloating wordlines in the unselected blocks are boosted to nearly theerase voltage Vers, which can be about 90% of Vers when the substrate ofthe cell array is biased to Vers, by capacitive coupling between thesubstrate and the wordlines when Vers is applied to the substrate. It isnoted that the actual boosted voltage level on the floating wordlines isdetermined by the coupling ratio between the substrate and wordlines.The boosted voltage on the wordlines in unselected blocks reduces theelectric field between the substrate and wordlines, thereby inhibitingerasure of the memory cells. Further details of wordline boosting inflash memory is described in commonly owned U.S. patent application Ser.No. 11/565,170 filed on Nov. 30, 2006, the contents of which areincorporated by reference.

TABLE 2 Selected Block Unselected Block Bitlines (B/L) Clamped to Vers -0.6 V Clamped to Vers - 0.6 V String Select Line (SSL) Boosted toapprox. 90% Boosted to approx. Vers 90% Vers Selected Wordline(s) 0 VBoosted to approx. 90% Vers Unselected Wordline Boosted to approx. 90%Boosted to approx. Vers 90% Vers Ground Select Line Boosted to approx.90% Boosted to approx. (GSL) Vers 90% Vers Common Source Line Clamped toVers - 0.6 V Clamped to Vers - (CSL) 0.6 V Substrate (Pocket Vers VersP-Well)

In the example of Table 2, the bias conditions are the same as thoseshown in Table 1, except that the unselected wordlines of the selectedblock are boosted to nearly the erase voltage Vers. In one embodiment,this boosted voltage is about 90% of Vers, which is achieved byprecharging the memory cells through the bitlines and source line, andthen boosting the wordlines through capacitive coupling to the substrateas it is raised to Vers. Once again, details of wordline boosting forinhibiting erase is described in detail in U.S. patent application Ser.No. 11/565,170. While the illustrated bias conditions shown in Tables 1and 2 are examples only, those skilled in the art should understand thatspecific values will depend on the manufacturing process, materialsused, and specific design of the memory cells.

Once a sub-block of a physical block has been erased, an optionalprocedure to be executed before data is reprogrammed, is an erase verifyoperation. The erase verify operation ensures that the erased cells havea threshold voltage proper threshold voltage margin. For example, theerase threshold voltage will be some negative voltage value. Intraditional block erase architectures, erase verify is executed bybiasing all the wordlines of the block to 0V, and sensing a currentthrough the NAND memory cell strings. Any memory cell having at leastone memory cell with an erase threshold voltage greater than 0V will notturn on, and the absence of a current in the corresponding bitlines willbe sensed. This traditional scheme is not possible when some of thememory cells still retain data corresponding to one of many possiblethreshold voltages.

According to an embodiment, an erase verify operation for a partiallyerased block is executed by biasing the selected wordlines coupled tothe erased memory cells to a voltage greater than the erase thresholdvoltage, and by biasing all remaining unselected wordlines to a voltageused for read operations. This voltage is referred to as Vread, and canrange between 4-5V for example. Table 3 shows example bias conditionsfor performing an erase verify operation on a partially erased block.

TABLE 3 Page Erase Verify with Source Bias Bitlines (B/L) Precharged andSensed String Select Line (SSL) Vread (4~5 V) Selected Wordlines 0 VUnselected Wordlines Vread (4~5 V) Ground Select Line (GSL) Vread (4~5V) Common Source Line Vcs (CSL) Substrate (Pocket P-Well) 0 V

According to an embodiment, the voltage of the source line (Vcs) isadjustable relative to the number of wordlines that are being verified,in order to ensure that the negative threshold erase voltage issufficiently spaced from 0V. For example, if the negative thresholderase voltage should be at least −0.5V, and erasing results in athreshold of −0.2V, then the wordline should be biased to −0.5V todetect the −0.2V threshold. However, since negative voltages may not besuitable for use in some devices, the source line Vcs is raised to apositive voltage level while the selected wordlines are biased to 0V. Bybiasing the Vcs positively, the selected wordline becomes effectivelynegative. Those skilled in the art should understand this effect.

FIG. 5 shows the relationship between the number of selected wordlinescorresponding to the erased sub-block being verified. The x-axis is thetotal number of wordlines to be verified while the y-axis is the voltageof common source line (Vcs). Diagonal curve 120 represents an idealrelationship between the voltage level of Vcs and the number of selectedwordlines. It is clear that the Vcs voltage decreases as the number ofselected wordlines to be verified increases. If only one wordline is tobe verified, then Vcs can be set to a first voltage, such as 0.4V forexample. On the other extreme, if all the wordlines are to be verified,then Vcs can be set to a second, smaller voltage of 0V. Therefore therange of Vcs in the presently shown embodiment can range between 0V and0.4V. In alternate embodiments having more wordlines in each NAND memorycell string, a voltage higher than 0.4V may be used.

Although diagonal curve 120 is ideal, the fine control required toimplement it in at least some examples is impractical. However, steppedvoltages for groupings of selected wordlines can be practicallyimplemented in source line voltage control circuit 104, as should beunderstood by those skilled in the art. Stepped curve 122 illustratesone example of the step sizes and wordline groupings that is possible.The selection of the first voltage, second voltage, size of wordlinegroupings and voltage step size between groupings, will be based on thedesign parameters of the flash memory device.

A partial block erase and erase verify method embodiment will now bedescribed with reference to FIG. 6. The method of FIG. 6 can be executedfor each partial block erase operation. The method begins at step 200 bysetting an erase loop counter variable, called ERS_LOOP equal to 1, orany desired starting value. At step 202, a partial block erase operationis executed for erasing at least one memory cell in a NAND memory cellstring. This step will include receiving a partial erase instruction,receiving address(es) corresponding to the memory cell(s) to be erased,biasing of the selected wordline(s), the unselected wordline(s),bitlines and other relevant signals to levels sufficient for erasing thememory cells coupled to the selected wordlines. Previously shown Tables1 and 2 list example bias values that can be used.

Now, the erase verify sequence begins at step 204 after a sub-block of aphysical block has been partially erased. This step will include settingof the appropriate Vcs level based on the number of selected wordlines,and biasing the selected and the unselected wordlines with theappropriate voltages for sensing the erased state of the memory cellscoupled to the selected wordlines. Previously shown Table 3 listsexample bias values that can be used. The bitline is precharged andsensing of the bitline is initiated. At step 206, sensing is completedand the result will indicate that the partial erase operation was eithersuccessful or not. For example, by biasing the selected wordlines to 0Vand biasing the unselected wordlines, SSL and GSL to Vread, thecorresponding bitline precharged to a high voltage level will dischargeto Vcs if all the memory cells coupled to the selected wordlines have athreshold voltage less than 0V, thereby passing the test. However, if atleast one memory cell coupled to the selected wordlines has a higherthan 0V threshold, then the bitline will not be discharged to Vcs,thereby failing the test. Either case can be detected by bitline senseamplifier circuits, as should be well known to those skilled in the art.

If the test is failed, then the method proceeds to step 208 where thecounter variable ERS_LOOP is compared to a maximum value, Max. If thecurrent loop counter is less than Max, then the ERS_LOOP is incrementedat step 210. From step 210, the method returns to step 202 and thepartial erase of the selected sub-block is repeated. Partial erase andverify steps 202, 204, 206, 208 and 210 will continue until one of twoconditions is met. The first condition occurs if counter variableERS_LOOP reaches the maximum value Max, then the method proceeds to step212 where the status register is updated to reflect a failed erasestatus. Alternately, all the pages corresponding to the sub-block aremapped out from further use. Then the method ends at step 214. Thesecond condition occurs if the test is passed, then the method proceedsfrom step 206 to step 216 where the status registers are updated toreflect a passed erase status. This sub-block is then ready to beprogrammed with new data.

In summary, the partial erase concept has been generally described withreference to the embodiments shown in FIGS. 3 to 6. By partially erasinga memory block, the flash memory device can create smaller subdivisionswithin the memory block, referred to as sub-blocks. Data occupying asub-block can be modified without having to erase the entire memoryblock, thereby conserving program/erase cycles and increasing thelife-span of the memory block. The following description discusses how aparticular sub-block is selected to be erased.

When any sub-block of the memory block is to be erased, the flash memorydevice will require information about its location within the memoryblock, so that it will know which rows (wordlines) to select forapplication of the bias voltages for effecting erasure of the memorycells coupled thereto. FIGS. 7 a to 7 c illustrate three possiblesize/locations of an erasable sub-block within a memory block.

FIG. 7 a is a circuit schematic of a NAND memory cell string that isprogrammed in sequence starting from WL₀ up to WL31. In this embodiment,the flash memory device only requires one wordline address as thestarting address. Once the starting address is received, the logic ofthe flash memory device will automatically set the sub-block size to befrom the starting address up to the last wordline, WL31 in this example.To illustrate with reference to FIG. 7 a, if the starting addresscorresponding to WL₂₇ is received for a partial erase operation, thenthe logic of the flash memory device will decide that the sub-block 300will start at WL₂₇ and end at WL₃₁. In other words, the end address ispreset to be WL₃₁ regardless of the starting address that is provided.Once the set of wordlines for the sub-block 300 is determined, then thepartial erase and erase verify procedures can be executed by biasing theselected and unselected wordlines. Sub-block 300 is an upper sub-block,where an upper sub-block is any grouping of wordlines including the lastwordline to be sequentially programmed.

FIG. 7 b is a circuit schematic of the NAND memory cell string of FIG. 7a. Similar to the embodiment of FIG. 7 a, only one starting row addressis required for a partial erase operation. In this embodiment, the logicof the flash memory device will automatically set the sub-block size tobe from the starting address down to the first wordline, WL₀. Toillustrate with reference to FIG. 7 b, if the starting addresscorresponding to WL₂₆ is received for a partial erase operation, thenthe logic of the flash memory device will decide that the sub-block 302will start at WL₂₆ and end at WL₀. The end address is preset to be WL₀regardless of the starting address that is provided. Sub-block 302 is alower sub-block, where a lower sub-block is any grouping of wordlinesincluding the first wordline to be sequentially programmed.

Both the embodiments of FIGS. 7 a and 7 b will subdivide one memoryblock into a lower sub-block and an upper sub-block. However, if onesub-block is erased and only partially re-programmed with data, therewill be pages still in the erased state. Further erasing of the originalsub-block will subject the erased pages to further erase operations,which is undesired. Therefore, a sub-block slice can be selected, asshown in the embodiment of FIG. 7 c.

FIG. 7 c is a circuit schematic of the NAND memory cell string of FIG. 7a. Now, a starting address and an ending address defines the sub-blockposition and size within the memory block. In this embodiment, the logicof the flash memory device will automatically set the sub-block size tobe from the starting address up to the ending address. To illustratewith reference to FIG. 7 c, if the starting address corresponding to WL₂and an ending address corresponding to WL₂₈ is received for a partialerase operation, then the logic of the flash memory device will decidethat the sub-block slice 304 will start at WL₂ and end at WL₂₈. Asub-block slice is any grouping of wordlines positioned between otherwordlines of the NAND memory cell string. To minimize program disturb,sub-block slice 304 can be repeatedly erased and programmed providedpages corresponding to WL₂₉ to WL₃₁ are erased, even if there is datastored in pages corresponding to WL₀ and WL₁.

As shown in FIGS. 7 a-7 c, at least one address is used for erasing anupper or a lower sub-block, while two addresses are used for erasing asub-block slice. According to an embodiment, a command protocol isprovided to allow a flash memory controller to interface with the flashmemory device and initiate erasing of an upper sub-block, a lowersub-block or a sub-block slice. Those skilled in the art will understandthat one or more flash memory devices can be controlled by a singleflash memory controller, which acts as an interface between the flashmemory device(s) and the host system, such as a computer.

FIG. 8 is a flow chart illustrating a command protocol embodiment forerasing a sub-block of a memory block. It is assumed that the flashmemory control logic, which may be implemented in control circuit 12 ofFIG. 1, is configured for responding to the present command protocol. Toexecute a partial erase operation upon a memory block, the flash memorycontroller first issues an address input command including a firstaddress at step 400. Following at step 402, the flash memory controllerissues another address input command including a second address. As willbe described in further detail later, the first or the second addresscan be a null address value. A partial erase command is issued at step404, and depending on the first and second addresses that werepreviously received, an upper sub-block, a lower sub-block, or asub-block slice is erased at step 406. Erasing at step 406 includesbiasing the wordlines, bitlines and source lines to their appropriatevoltage levels.

In this command protocol example, three address combinations areallowed. In a first case, when the first address is valid and the secondaddress is null, the control logic will select an upper sub-block boundby and including the wordline corresponding to the first address(referred to as an intermediate wordline between the first and lastwordline of the NAND memory cell chain) to the last wordline of the NANDmemory cell string, ie. WL₃₁ in the present example. In a second case,when the first address is null and the second address is valid, thecontrol logic will select a lower sub-block bound by and including theintermediate wordline corresponding to the second address to the firstwordline of the NAND memory cell string, ie. WL₀ in the present example.In a third case, when the first and second addresses are valid, thecontrol logic will select a sub-block slice bound by and including thewordlines corresponding to the first and second addresses. Those skilledin the art will appreciate that the three situations listed aboverepresents one possible protocol configuration. In one alternateconfiguration, the first case will result in a selection of a lowersub-block while the second case will result in a selection of an uppersub-block. In yet another alternate embodiment, the partial erasecommand can be issued before either the first and second input addresscommands are issued.

FIG. 9 is a flow chart of a specific method embodiment for erasingeither an upper sub-block, a lower sub-block, or a sub-block slice usingthe command protocol shown in FIG. 8. More specifically, one of an uppersub-block, a lower sub-block, and a sub-block slice is erased based onthe presence or absence of a first or second valid address received withthe first input address command and the second input address command.For the purposes of the following description, it is assumed that theflash controller is configured for issuing a partial erase command forerasing sub-blocks of memory blocks of a flash memory device, and thatthe flash memory device includes the control logic for biasing thewordlines, bitlines and other signals for partial erase and erase verifyoperations.

The method of FIG. 9 illustrates the logical operation of the flashmemory device control logic in response to address input commands and anerase command, according to the command protocol of FIG. 8. The methodof FIG. 9 begins at step 500, where a first address input command isreceived. This address input command will include either a first validaddress corresponding to a wordline of the NAND memory cell string ofthe memory block, or a null address. In the first case, the firstaddress is valid and the method proceeds to step 502, where a secondaddress input command is received with a second address. The secondaddress can be a valid address corresponding to a different wordline ofthe NAND memory cell string, or a null address. Continuing with thefirst case, the second address is the null address and the methodproceeds to step 504. At step 504 a partial erase command is receivedand the upper sub-block is erased and verified at step 506. Step 504includes appropriate biasing of the wordlines, bitlines and otherrelevant signals for erasing the upper sub-block and erase verifying theupper sub-block.

Returning to step 500, if the first address is the null address insteadof a valid address, the method proceeds to step 508, which is the sameas step 502. If the second address is also a null address, then thepartial erase method ends and returns to step 500. On the other hand, ifthe second address is a valid address, then case 2 occurs. Once apartial erase command is received at step 510, a lower sub-block iserased and verified at step 512. Step 512 includes appropriate biasingof the wordlines, bitlines and other relevant signals for erasing thelow sub-block and erase verifying the lower sub-block. Returning to step502, if the first address from step 500 is valid and the second addressis valid, then case 3 occurs. The method then proceeds to step 514 wherethe partial erase command is received. Then a sub-block slice is erasedand verified at step 516. Step 516 includes appropriate biasing of thewordlines, bitlines and other relevant signals for erasing the sub-blockslice and erase verifying the sub-block slice.

While the command protocol does not require a second valid address forcase 1 or a first valid address for case 2, the command protocol can beconfigured to accept valid second and first addresses for cases 1 and 2respectively. For example, to erase an upper sub-block, the firstaddress will correspond to an intermediate wordline while the secondvalid address corresponds to the last wordline WL₃₁, for example.Similarly, to erase a lower sub-block, the first address will correspondto the first wordline WL₀, while the second valid address corresponds toan intermediate wordline.

Therefore, by using the command protocol and method shown in FIGS. 8 and9, any arbitrary sub-block of a memory block can be repeatedly erasedand re-programmed with data without impacting the program erase cyclelifespan of the other sub-block or sub-blocks of the memory array. Anyflash memory device or flash memory system having one or more flashmemory devices, configured for erasing arbitrary sub-blocks can becontrolled to execute wear leveling algorithms for maximizing thelifespan of memory blocks, thereby maximizing the lifespan of the flashmemory device. A flash memory device operating without a wear levelingalgorithm will program data sequentially from a first memory block to alast memory block, filling each memory block before programming the nextone. Uneven wear will result if the system continuously programs anderases data in the first memory block, leaving the other memory blocksunused.

Wear leveling is a scheme for ensuring even use of all the memory of aflash memory device. More specifically, wear leveling ensures that allthe memory blocks experience substantially the same number of programcycles or erase cycles. Those skilled in the art will understand thatflash memory cells can be programmed/erased a finite number of timesbefore data is no longer reliably stored. A flash controller tracks thetotal number of program/erase cycles experienced by each memory block orpage of the memory block. The number of cycles is stored in a sparefield of each page of the memory array. The flash controller will map alogical address location of data to a physical address where the data isstored in the flash memory device. When a memory block has reached amaximum predetermined number of program/erase cycles, the flashcontroller will instruct the flash memory device to reprogram the datastored in the memory block to an available memory block, and then mapsout the original memory block from further use (now called an invalidblock). The mapping is then adjusted accordingly.

Presently known wear leveling techniques employ logical to physicalmapping techniques for programming data across different memory blocks.For example, a large data file to be programmed can have a first portionprogrammed to a first block, a second portion programmed to a secondblock, and so forth. In another example, multiple data files totalingless than the size of one memory block can be each programmed todifferent memory blocks. Hence, if a specific portion of the large datafile, or a specific small data file is to be modified, only thecorresponding memory block storing it would be subjected to aprogram/erase cycle. The problem with all these schemes is thatmodifying a small data file or a portion of a data file residing in amemory block requires erasing the entire memory block. Therefore, theother data stored in the memory block will also be erased, andunnecessarily reprogrammed as the modified data is reprogrammed. This isa primary factor that will contribute to a reduction in the lifespan ofthe memory blocks.

In the previously described example embodiments, the sub-block to beerased was an arbitrary size, determined by the data in the memory blockto be erased or modified. Modifying the data of the sub-block can bedone by erasing the sub-block and reprogramming it with the modifieddata. However, this may subject the sub-block to too many program/erasecycles, thereby prematurely decreasing its lifespan relative to unusedsub-blocks. Therefore, according to another embodiment, a wear levelingalgorithm taking advantage of erasable sub-blocks to minimizeunnecessary program/erase cycles is provided.

The present wear leveling algorithm will have the memory blocks of theflash memory device to be logically divided into predeterminedsub-blocks. FIG. 10 a illustrates an example where a memory block 600 isdivided into two equally sized sub-blocks, sub-block 0 and sub-block 1.Sub-block 0 consists of pages 0 to 15 while sub-block 1 consists ofpages 16 to 31. It is assumed that the memory block is programmedsequentially from page 0 to page 31, where each page corresponds to aspecific wordline. FIG. 10 b illustrates an example where a memory block602 is divided into four equally sized sub-blocks, sub-block 0,sub-block 1, sub-block 2 and sub-block 3. Alternately, the sub-blocks ofthe memory blocks 600 and 602 do not necessarily have to be divided intoequal sizes, and thus can have different predetermined sizes. Once thelogical sub-blocks are determined, data can be programmed according tothe wear leveling algorithm.

As previously discussed, a NAND memory cell string sequentiallyprogrammed with data from WL₀ to WL₃₁ (or alternately from WL₃₁ to WL₀)will experience minimum program disturb provided there is no data in thepages above the sub-block to be programmed. In the present example, apage above the sub-block will correspond to a wordline having a highernumber. Accordingly in the example of FIG. 10 a, sub-block 0 is referredto as a lower sub-block while sub-block 1 is referred to as an uppersub-block. In the wear leveling algorithm of the present embodiment,data will not be programmed to a lower sub-block if there is dataresiding in an upper sub-block. The flash memory controller will knowthat there is data in an upper sub-block by referring to the addressmapping table which can include one or more validity bits loaded fromthe spare field of each page of the lower sub-block. A specific logicstate of the validity bits will indicate to the flash memory controllerwhether or not the lower sub-block can be programmed. Alternately, thevalidity bits of the spare field corresponding to the upper sub-blockwill indicate that data will not be programmed to the lower sub-block.In the example of FIG. 10 b, a sub-block of a pair of adjacentsub-blocks having a higher number is an upper sub-block while the otherhaving a smaller number is a lower sub-block. In a memory blockconfigured to have more than two sub-blocks as shown in FIG. 10 b,sub-block 0 is the lowest ranking sub-block while sub-block 3 is thehighest ranking sub-block and data will not be programmed to a sub-blockif there is data stored in any sub-block having a higher ranking.

The wear leveling algorithm of the present embodiment shown in FIG. 11will include a data programming sub-routine for programming new data tothe flash memory device and a data modification sub-routine forre-programming modified data to the flash memory device. Bothsub-routines ensure that the sub-blocks of the flash memory device areevenly used. The wear leveling algorithm is executed by the flash memorycontroller for a flash memory device configured for erasing sub-blocksof predetermined sizes, and begins at step 700 by receiving a commandfrom the host system. At step 702, the flash memory controllerdetermines if the command is to program new data or to modify currentlyprogrammed data. If the command is to program new data, the methodproceeds to step 704 where the data is programmed to the lowest rankingavailable sub-block. For example, if the flash memory device consists offour empty memory blocks, each logically divided into two sub-blocks(sub-block 0 and sub-block 1) as shown in FIG. 10 a, then data issuccessively programmed to sub-block 0 of every memory block.Eventually, all sub-block 0's will store data, and the next data to beprogrammed will be programmed to the first available sub-block 1.

By programming new data to the lowest available sub-blocks first, allthe memory blocks will be used. However, step 704 can be replaced withan alternate data programming scheme. In this alternate scheme,programming new data will be based on a high or low priority level ofthe data to be programmed. The host system may decide that music filesand executable applications with the appropriate file extensions arehigh priority, while data files such as text documents that arefrequently modified, are low priority. The designation of data as highor low priority can be arbitrarily set by the host system.

In the alternate data programming embodiment, step 704 is replaced witha determination step for the priority level of the data. If the data isdesignated as high priority, it is programmed to the lowest availableranking sub-block of a memory block, since a high priority data file isless likely to be modified over time. If the lowest available rankinglower sub-block is too small to store the data, then the high prioritydata can be divided and distributed across two or more lowest rankingavailable sub-blocks of different memory blocks. Alternately, the datacan be programmed to any number of adjacent lowest ranking availablesub-blocks within the same memory block. If the data is designated aslow priority, it is programmed to the highest available rankingsub-block of a memory block, since a low priority data file is morelikely to be modified over time. If the sub-block is too small, then thedata can be distributed in the same manner as previously described forthe high priority data.

Returning to step 702, if the command is for modifying previouslyprogrammed data, the method proceeds to step 710. Since the previouslyprogrammed data resides in a sub-block of a memory block, that sub-blockcan be erased and reprogrammed with the modified data. If the sub-blockincluded other data files, then they are re-programmed at the same time.However, the sub-block erase operation that must be executed beforere-programming will slow performance of the flash memory device, andwill subject the sub-block to a program/erase cycle. To overcome bothproblems, the modified data of the original sub-block is programmed toanother sub-block in a different memory block at step 710. The originaladdress mapping table maintained by the flash memory controller is thenadjusted at step 712 to indicate that the data stored in the sub-blockof the original memory block is now physically located in the sub-blockof a new memory block. Later when the system is idle, the sub-blockwhere the data was originally stored is erased at step 714, and thiserased sub-block is marked as erased and available for storing data. Thestep of erasing can follow the method previously described in FIG. 9. Byerasing the sub-block later, programming performance is maximized.

Re-programming the modified data in step 710 is further managed by afree sub-block allocator sub-routine. This sub-routine will identify themost appropriate sub-block to re-program the data to, based on thestatus of the other memory blocks of the flash memory device. Thesub-block allocator sub-routine embodiment will re-program data of asub-block to a sub-block in another memory block, with a priority tofirst re-program the data to a matching physical sub-block (ie. samesub-block ranking). If a matching physical sub-block is unavailable,then the data is re-programmed to the next most suitable physicalsub-block. The purpose of matching sub-blocks is to maintain, as much aspossible, the distribution of high and low priority data according tothe selective data distribution algorithm described in FIG. 11 so thatlow priority data is programmed to higher ranking sub-blocks. Thesub-block allocator sub-routine method will be described with referenceto the flow chart of FIG. 12, and the graphical illustration of anoriginal memory block and a new memory block in FIGS. 13 a to 13 d.

The method of FIG. 12 starts when a command for modifying data isreceived at step 800. The command will include information pertaining tothe address location of the sub-block of the original memory block thatthe data to be modified currently resides within. At step 802, the othermemory blocks are logically sorted according to a predetermined orderingscheme to determine the sequence of memory blocks to assess. Forexample, the simplest scheme is to set the order based on the assignedphysical/logical position of the memory blocks. A second scheme is toset the order based on the occupancy rate of the memory blocks, forexample from fully empty blocks to fully programmed blocks or viceversa. A third scheme is to set the order based on the memory blockswith the least number of program/erase cycles. The second and thirdschemes can be implemented by scanning the address mapping table of thememory blocks, which will indicate the sub-blocks that are empty and thenumber of program/erase cycles of each page or memory block. Thislogical sorting can be dynamically maintained as data is programmed anderased from the memory blocks.

Then the method will assess the first new memory block in the logicallysorted list of memory blocks and determine if the data should bere-programmed to it. At step 804 the method checks if the new memoryblock has an available matching physical sub-block, ie. a sub-block ofthe same ranking that is erased. If one is present in the new memoryblock, then the system checks if there are any sub-blocks of higherranking than the sub-block presently storing the original data at step806. To minimize program disturb, the data is not re-programmed to thematching physical sub-block when there are higher ranking sub-blockswith data stored therein. If a higher ranking sub-block with dataexists, then the method assesses the next memory block in step 808 andreturns to step 804. Otherwise, the other sub-blocks storing data are oflower ranking, and the method proceeds to step 810 to determine if thenew memory block is empty. If the memory block is not empty, then thereis data programmed to one or more lower ranking sub-blocks and the datais re-programmed to the matching sub-block of the new memory block instep 812.

By example, FIG. 13 a shows an original memory block 900 configured tohave sub-blocks 0 to 3, and a new memory block 902 to be assessed, whichis also configured to have sub-blocks 0 to 3. Pages with hatchingindicate the presence of data, and pages without hatching are empty andpreviously erased. Assuming that the data of sub-block 1 is to bemodified, a matching sub-block 1 is found in memory block 902, whichincludes data programmed in lower ranking sub-block 0. Since there areno higher ranking sub-blocks with programmed data in memory block 902,the data is programmed to sub-block 1 of memory block 902.

Returning to step 810, if the new memory block is empty, then the datais re-programmed to the first sub-block (sub-block 0) of the memoryblock at step 814. FIG. 13 b shows original memory block 900 configuredto have sub-blocks 0 to 3, and a new memory block 904 to be assessed,which is also configured to have sub-blocks 0 to 3. In this example,memory block 904 is empty, and the data is programmed to sub-block 0 ofempty memory block 904.

In an alternative embodiment, step 810 can be omitted and the data willbe programmed to the matching sub-block if the new memory block isempty. According to another alternative embodiment, memory block usageis maximized by including another step to ensure that the new memoryblock has all its lower ranking sub-blocks populated with data.

Previously described steps 806, 808, 810, 812 and 814 are the methodsteps executed if there is a matching sub-block in the new memory block.A situation may arise where all the available memory blocks have higherranking sub-blocks programmed with data, as determined throughiterations of steps 804, 806 and 808. In such a case, the method treatthe memory blocks as not having an available matching sub-block.Returning to step 804, if there are no matching physical sub-blocks,then the method proceeds to step 816 for re-programming the data to asub-block of a higher ranking than the sub-block currently storing thedata to be modified. The data can be programmed to the first availablehigher ranking sub-block or to the lowest ranking sub-block that isavailable. FIGS. 13 c and 13 d illustrate cases where the data isre-programmed to a higher ranking sub-block.

FIG. 13 c shows original memory block 900 configured to have sub-blocks0 to 3, and a new memory block 906, both configured to have sub-blocks 0to 3. In this example, sub-block 1 of memory block 906 currently storesdata, thus the data of sub-block 1 of memory block 900 is programmed tosub-block 0 of empty memory block 904. FIG. 13 d shows the same memoryblock 900 and a new memory block 908, both configured to have sub-blocks0 to 3. In this example, sub-block 1 of memory block 908 is empty buthigher ranking sub-block 2 stores other data. Therefore, the data isre-programmed to the next highest available sub-block, sub-block 3 inmemory block 908.

During the lifetime of the flash memory device, the flash memorycontroller will monitor the number of program/erase cycles accumulatedby each sub-block, which will occur as new data is programmed and olddata is modified. Certain sub-blocks in a memory block may have a highernumber of program/erase cycles than the other sub-blocks in the memoryblock. This leads to an imbalance of program/erase cycles between thesub-blocks of the memory block. According to another embodiment, data inthe sub-blocks of the memory block can be swapped or moved to differentmemory blocks when predetermined conditions are met. One such criteriacan be a predetermined difference of program/erase cycles between thesub-blocks, for example.

FIG. 14 is a flow chart of a general method for controllingprogram/erase cycle imbalance between sub-blocks of a memory block. Themethod can be initiated upon power up of the flash memory device, or atany arbitrary time while the flash memory device is powered up, and isexecuted by the flash memory controller. At step 1000, the number ofprogram/erase cycles for every pair of sub-blocks in a memory block isscanned. Those skilled in the art will understand that one or more pagesof each sub-block will store a counter in a spare field areacorresponding to the number of program/erase cycles it has beensubjected to. These counter values are read and loaded into the addressmapping table of the flash memory controller. At step 1002, a check ofthe program/erase cycle count for each sub-block of the memory block ismade. If the program/erase cycle count has reached the maximum allowedvalue, then the data stored therein is copied to an available sub-blockat step 1004 and the original sub-block is retired or mapped out fromfurther use at step 1006. The copying step of 1004 can follow the methodoutlined in FIGS. 11 and 12.

Otherwise, the process proceeds to step 1008 where the differencebetween the sub-block with the highest program/erase count and thesub-block with the lowest program/erase count is calculated to beΔCycles. If ΔCycles is less than the set limit called “Set_diff”, thenthe method loops back to step 1002 and the next memory block isassessed. On the other hand, if ΔCycles is at least “Set_diff”, then themethod proceeds to step 1010 where the data in the two sub-blocks areswapped with each other. The value of “Set_diff” is set by themanufacturer of the flash memory system, or the flash memory controller,according to the manufacturer flash management policy. Sub-blockswapping of step 1010 is executed by first copying the data stored inall the sub-blocks of the memory block to an available physical block orother available sub-blocks. The original memory block is erased and thedata is re-programmed to the sub-blocks of the memory block such thatthe data of the two sub-blocks are swapped. The other memory block, orthe available sub-blocks, acting as temporary storage for the data canbe erased at any time by a full memory block erase or a partial erase aspreviously taught. The address mapping table is then updated to reflectthe change in the physical location of the swapped data.

FIG. 15 a shows an original memory block 1100 configured to havesub-blocks 0 to 3, where sub-block 0 stores data DATA A, sub-block 1stores DATA B, sub-block 2 stores DATA C and sub-block 3 stores DATA D.If sub-blocks 0 and 3 are determined to have ΔCycles>“Set_diff”, thenthe data is swapped. FIG. 15 b shows the resulting data mapping inmemory block 1100 after data swapping. Now sub-block 0 stores DATA D andsub-block 3 stores DATA A.

Once the data of all the memory blocks have been swapped, normalprogramming operations can proceed. For example, new data can beprogrammed to the flash memory device and existing data can be modified.

The previously described embodiments allow for selective erasing ofportions of a memory block, called a sub-block, by biasing wordlinesbitlines and other relevant signals. The life-span of a memory block maytherefore extended since only the sub-block where data is modified issubjected to a program/erase cycle. The sub-blocks can be arbitrary insize, or preset to be specific sizes. A command protocol is provided toallow a flash memory controller to interface with the flash memorydevice and initiate erasing of arbitrarily sized sub-blocks and presetsized sub-blocks. This command protocol can then be used for executing awear leveling algorithm when programming new data to the flash memorydevice, or when modifying existing data stored in the flash memorydevice. All these aspects can be used by themselves or in combinationfor extending the life-span of memory blocks.

The previously described embodiments have been described with referenceto memory blocks having two or four sub-blocks therein. However, theembodiments are applicable to memory blocks logically divisible into anynumber of sub-blocks.

In the preceding description, for purposes of explanation, numerousdetails are set forth in order to provide a thorough understanding ofthe embodiments. However, it will be apparent to one skilled in the artthat these specific details are not required in order to practice theembodiments. In other instances, well-known electrical structures andcircuits are shown in block diagram form in order not to obscure theaspects of the embodiments. For example, specific details are notprovided as to whether the embodiments described herein are implementedas a software routine, hardware circuit, firmware, or a combinationthereof.

The above-described embodiments are intended to be examples only.Alterations, modifications and variations can be effected to theparticular embodiments by those of skill in the art without departingfrom the scope, which is defined solely by the claims appended hereto.

What is claimed is:
 1. (canceled)
 2. A method for erasing a sub-block ofa memory block, the memory block having a NANO memory cell stringcoupled to a first wordline, a last wordline, and intermediate wordlinesbetween the first wordline and the last wordline, comprising issuing afirst input address command with a first address; issuing a second inputaddress command with a second address; issuing a partial erase command;and, erasing the sub-block having a set of wordlines bound by word linescorresponding to the first address and the second address.
 3. The methodof claim 2, wherein the first address includes a null address.
 4. Themethod of claim 3, wherein the sub-block includes the set of word linesbound by one wordline corresponding to the second address and the firstwordline.
 5. The method of claim 2, wherein the second address includesa null address.
 6. The method of claim 5, wherein the sub-block includesthe set of wordlines bound by one wordline corresponding to the firstaddress and the last wordline.
 7. The method of claim 2, furtherincluding erase verifying the erased sub-block.
 8. The method of claim7, wherein erase verifying includes precharging a bitline coupled to theNANO memory cell string to a precharge voltage level, biasing the set ofword lines to a first voltage for turning on erased memory cells coupledto the set of word lines, biasing unselected wordlines to a secondvoltage for turning on memory cells coupled to the unselected wordlines,and sensing a change in the precharge voltage level.
 9. The method ofclaim 8, wherein the first voltage is a negative voltage and the secondvoltage is a read voltage used during a read operation.
 10. The methodof claim 8, wherein the first voltage is 0V and the second voltage is aread voltage used during a read operation.
 11. The method of claim 10,wherein a common source line coupled to the NANO memory cell string isbiased to a variable source bias voltage.
 12. The method of claim 11,wherein the variable source bias voltage increases from 0V to a maximumvoltage as a number of the set of word lines decreases.